00100		HARDWARE.
00200	
00300	Dual port ram interface.
00400	
00500		The dual port ram is implemented as a dual port data bus.
00600	On each joint processor's data bus there is an 8 bit transiver
00700	connected to an 8 bit host - joint I/O bus that is controled by the
00800	host interface. When reading or writing data from a joint's memory,
00900	the host interface first addresses the joint. Then when the host reads
01000	or writes data to/from the interface, the interface waits for the joint
01100	processor's bus to be not locked and a joint instruction fetch signal.
01200	A joint's data bus is locked when the joint reads or writes an area of
01300	memory (shared memory), at an even address. The bus is unlocked when
01400	a read or write is preformed on an odd address. Waiting for a joint
01500	instruction fetch insures that the joint processor will not access
01600	the location being read or writen by the host before the host is
01700	finished.
01800	
01900	Each joint processor's data memory consists of:
02000	
02100		Read write memory. 1024 by 8 bits of moderatly fast (200 n.s.)
02200	mos memory.
02300	
02400		Address and control multiplexers. Twelve 2 line to 1 line data
02500	selectors.
02600	
02700		Data bus transiver.
02800	
02900		Bus lockout logic. Which is simply the least significant
03000	address bit of the joint processor clocked by an access to shared ram
03100	by the joint processor.
03200	
03300		Host - joint clock synchronizer. Which, during the joint phase,
03400	streches the ram CS signal until the falling edge of the joint's phase
03500	two clock.
03600	
03700	
03800	Processor and I/O.
03900	
04000		The encoder interface is a three state 2 to 1 multiplexer.
04100	The processor, output port, DAC, and EPROM program memory are standard
04200	except that the address decoding is only enabled during the phase two
04300	portion of the clock.
04400	
04500	Host - joint interface.
04600	
04700		The host - joint interface is the same as the earlier design
04800	except that the joint memory read/write logic has been added and the
04900	ADC and attention request logic have been removed.
     

00100		SOFTWARE.
00200	
00300		The basic servo routine remains the same as the earlier
00400	design. Parts of the program that are changed, new, or deleted are:
00500	
00600		The locations of data in ram are changed for the shared ram.
00700	
00800		All of the old position encoder routines have been replaced by
00900	the GETPOS routine which reads the parallel encoder and converts it
01000	from grey to binary.
01100	
01200		The PUTDAC routine has been changed from 12 bits to 8.
01300	
01400		All immediate commands have been deleted.
01500	
01600		The deferred command dispatcher has been changed and a
01700	host - joint deferred command interface routine has been added to
01800	the idle loop.
01900	
02000		The VETBL has been added to correct the dac output.
02100	
02200		The freeze routine has been moved into the reset routine
02300	and is no longer a subroutine.
02400	
02500		All of the 6532 timer and I/O routines have been deleted.
02600	
02700		NMI is no longer being used.
02800	
02900		All accesses to shared ram are "unlocked" within 4 micro
03000	seconds after being locked and all 16 bit accesses to shared ram
03100	are done with the interrupt disabled.
     

00100		COMPARISON OF THE JOINT PROCESSORS.
00200	
00300		The new joint prcessor improves on the earlier design in the
00400	following ways:
00500	
00600		By allowing the host direct access to each joint processor's
00700	memory, all host - joint communication is much simpler and faster.
00800	Using shared ram allows reduced host wait time (at least 40%)
00900	when setting new servo position or other syncronized functions,
01000	and greatly reduced joint processor parameter passing overhead
01100	(about 80% less).
01200	
01300		Twice the basic processor cycle than the earlier standard
01400	board.
01500	
01600		Reduced parts count. By using an off board interval generator,
01700	simpler logic on each processor, etc.
01800	
01900		Micro bus compatible 8 bit DAC. What is lost in resolution
02000	(8 bits vs. 12 bits), is regained in speed, less parts, ease of use,
02100	etc.
02200	
02300		Simpler software. By using shared ram, absolute optical
02400	encoders, synchronous intervals, etc. much of the software is
02500	reduced or eliminated.
02600	
02700		Software compatible. By using the same processor and limited
02800	modification of the basic design (I/O and interface paths, etc.),
02900	the joint and host software is able to remain somewhat compatible
03000	with the earlier system.
03100	
03200		Although converting the encoder position from grey to binary
03300	requires an extra 50 micro seconds, the reduced overhead of the
03400	parallel encoder makes up for the delay.